The invention generally relates to MOS bootstrap circuits, and more particularly to MOS sample and hold circuits utilizing bootstrap circuitry, and still more particularly to pipeline analog-to-digital converters (ADCs) utilizing sample and hold circuits including MOS bootstrap circuitry.
CMOS sample and hold (S/H) circuits have been long used in pipeline analog-to-digital converters. See "A Pipeline 5-M sample/s 9-bit Analog-to-Digital Converter" by Steven H. Lewis and Paul R. Gray, IEEE J. Solid State Circuits, vol. SC-22, no. 6, pages 954-961, December 1987. Also see pages 542 and 543 of "Analog-digital conversion handbook", 1986, by Analog Devices, Inc., for a discussion of harmonic distortion of digital-to-analog converters. Also see the doctoral dissertation entitled "Video-Rate Analog-to-Digital Conversion Using Pipelined Architecture", dated Nov. 18, 1987, and related Memorandum No. UCB/ERL M87/90 therein by Stephen H. Lewis.
Pipeline ADCs are the type of ADC most commonly used for converting high frequency input signals to digital numbers. FIG. 1 shows a block diagram of a prior art 12-bit pipeline ADC architecture. Pipeline ADC 30 includes 11 identical or similar stages 30-1,2 . . . 11. The first stage 30-1 receives a differential high frequency input signal v.sub.in applied between the inputs of a differential sample and hold circuit 31-1. In the prior art, the differential input signal v.sub.in may be a signal varying from DC to only about 5 to 10 megahertz. Stages 30-2,3 . . . 10 of pipeline analog-to-digital converter 30 each include a DC sample and hold (S/H) circuit 31-2 . . . 10. Such S/H circuits are conventional. Each receives a differential DC error voltage from the previous stage. Note that only the input S/H circuit 31-1 has to acquire an AC signal. The remaining S/H circuits 31-2,3 . . . 10 simply acquire and hold the DC error voltages from the previous stages, respectively. The conventional input S/H circuit 31-1 in FIG. 1 limits the speed and linearity of the prior art pipeline ADC shown in FIG. 1.
Each stage of pipeline ADC 30 of FIG. 1 includes a 2-bit flash ADC (analog-to-digital converter) and a 2-bit DAC (digital-to-analog converter), and operates by successively performing "coarse" analog-to-digital conversion of the analog error terms produced by the successively preceding stages to generate successively less significant output bits B2-B12, respectively. Differential architectures usually have been used in the S/H circuits because they convert offset errors, charge injection errors, etc., to common mode signals which are inherently cancelled out by the differential amplifiers therein. As described in numerous publications by Professor Paul Gray and various students of the University of California at Berkeley over the past twenty or more years, pipeline ADCs have the advantage that non-critical circuit components can be used to form an analog-to-digital converter with very good resolution and very high accuracy. Recent literature has discussed development of high speed pipeline ADCs in the 10 to 16-bit range. At the current state of the art, attempts are being made to produce pipeline ADCs that can convert analog input signals of frequencies of higher than 20 megahertz to digital numbers with sufficiently good accuracy and resolution to be useful for very high speed applications.
To this end, it is important that the input S/H circuit 31-1 of prior art FIG. 1 be improved to have wider bandwidth so as to be able to accurately acquire and hold such high frequency analog input signals. (As a rule of thumb, the bandwidth of a high speed S/H circuit should be at least twenty times the clock frequency. It usually is desirable to obtain 0.1 LSB accuracy. The required number of time constants .tau. is given by ln(2.sup.N), where N is the number of bits of the ADC. Therefore, the total time (ln(2.sup.N))*.tau. is 1/2 f.sub.CLK if only half of the clock cycle is available for obtaining the 0.1 LSB accuracy. For N equal to 12 bits, ln(2.sup.N)=10.6, so .tau..apprxeq.20.multidot.f.sub.CLK is the sampling clock frequency.) While the S/H circuit 31-1 is holding the acquired (sampled) input signal, the second S/H circuit 31-2 is acquiring it, in a time-interleaved process controlled by two non-overlapping clock signals.
FIG. 2A shows a common differential S/H circuit 31, in which an analog input signal v.sub.in is applied between a (+) input terminal 41A and a (-) input terminal 41B, which are coupled by switches 42A and 42B to conductors 43A and 43B, respectively. Switches 42A and 42B are controlled by a clock signal .phi.1. Conductors 43A and 43B are connected to the "bottom" plates of sampling capacitors CS1 and CS2, respectively. A switch 44, controlled by a second clock phase .phi.2, is coupled between conductors 43A and 43B. As shown in FIG. 2B, .phi.1 and .phi.2 are non-overlapping clock signals which are derived from a main sampling clock signal CLK. The trailing edges of signals .phi.1A and .phi.1B are also shown in FIG. 2B. The "top" plates of sampling capacitors C.sub.S1 and C.sub.S2 are coupled by conductors 45A and 45B to the (+) and (-) inputs of an operational amplifier 47, which has an inverted output on conductor 51A and a non-inverted output on conductor 51B. A DC output signal V.sub.OUT appears between conductors 51A and 51B. A switch 46, controlled by a slightly delayed clock signal .phi.1A, is connected between conductors 45A and 45B.
A sampling capacitor C.sub.S3 is coupled between conductor 45A and conductor 49A. Similarly, a sampling capacitor C.sub.S4 is coupled between conductors 45B and 49B. Switches 48A and 48B, controlled by a delayed clock signal .phi.1B, are coupled between a bias voltage V.sub.B1 and conductors 45A and 45B, respectively. Conductors 49A and 49B are coupled by switches 50A and 50B, controlled by .phi.1, to a common mode voltage V.sub.CM. Conductors 49A and 49B also are connected by switches 52A and 52B, controlled by .phi.2, to output conductors 51A and 51B, respectively. During .phi.2, operational amplifier 47 is connected as a feedback amplifier, with switches 52A and 52B closed; switches 42A, 42B, 50A, 50B, 48A, and 48B also are open. Switch 44 is closed and switch 46 is open, so that the sampled charge on the series connection of C.sub.S1 and C.sub.S2 is redistributed onto sampling capacitors CS3 and CS4, respectively. v.sub.in is acquired or stored on the series connection of sampling capacitors C.sub.S1 and C.sub.S2 when switches 42A, 42B, and 46 are closed and switch 44 is open.
The differential S/H circuit shown in FIG. 2A is known by those skilled in the art to avoid clock feedthrough problems by "bottom plate switching" wherein switches 48A and 48B open first to remove the DC bias voltage V.sub.B1 from conductors 45A and 45B. Then switches 46, 42A, and 42B are opened. This results in very little charge injection into the bottom plate conductors 45A and 45B. After switches 48A and 48B are opened, switch 46 is opened, ending the acquisition mode. Finally, switches 42A and 42B are opened to remove the input signal from the top plates of sampling capacitors CS1 and CS2. This technique, known as bottom plate switching, results in minimal charge being injected into the top plates of the sampling capacitors.
All of the switches usually are implemented using MOS transistors. Switches 42A and 42B typically each are CMOS transmission gates. Therefore, if v.sub.in is a high frequency signal, the above mentioned problems caused by the nonlinear channel resistance of the sampling MOSFET switches 42A and 42B can produce inaccuracy in the sampled DC output voltage V.sub.OUT. Such inaccuracy generally cannot be compensated for later in a utilization circuit (such as a pipeline ADC).
To understand the bandwidth limitations of the above described prior art circuit of FIG. 2A, it may be helpful to refer to FIG. 2C, wherein a typical MOS S/H circuit of the type generally used in the circuits of FIGS. 1 and 2A includes a "sampling MOSFET" 35 coupled by its source and drain between an AC analog input signal v.sub.in and a "sampling capacitor" C.sub.S. The gate electrode of sampling MOSFET 35 receives a control signal V.sub.SAMPLE that is at a constant "1" level during an "acquire" or "sample" mode during which the voltage across the sampling capacitor C.sub.S follows or tracks the AC input signal v.sub.in. (The terms "sampling", "acquiring", and "tracking" as used herein all have essentially the same meaning.) When V.sub.SAMPLE undergoes a transition from a "1" or "acquire" level to a "0" or "hold" level, sampling MOSFET 35 is turned off. Thereafter, the voltage across sampling capacitor C.sub.S has a DC value nearly equal to the value of v.sub.in at the instant sampling MOSFET 35 was turned off.
During the "acquire" operation sampling MOSFET 35 is on, and therefore can be represented as a variable resistor having a channel resistance r.sub.on. r.sub.on is a strong function of the gate-to-source voltage of sampling MOSFET 35. The variation in r.sub.on causes a corresponding inverse variation in the bandwidth of the S/H circuit, which in turn results in substantial inaccuracies in the acquisition of the acquired values of v.sub.in if the sampling frequency is high, especially above 5-10 MHz. Therefore, at any high frequency of v.sub.in, the analog input signal v.sub.in never is perfectly acquired by sampling capacitor C.sub.S. The accuracy with which v.sub.in is acquired on sampling capacitor C.sub.S actually is a nonlinear function of v.sub.in, because of the nonlinearity of r.sub.on as a function of v.sub.in.
Consequently, if the S/H circuit is at the "front end" of a pipeline ADC, the variations in r.sub.on as a function of v.sub.in cause uncorrectable harmonic distortion in the digital output signal produced by the pipeline ADC.
In the prior art, one approach to avoiding such nonlinearity of the channel resistance r.sub.on of sampling MOSFET 35 as a function of v.sub.in is to make MOSFET 35 very large, so its r.sub.on is negligible. That approach has been suitable for pipeline ADCs which sample v.sub.in at no more than a 5 to 10 megahertz rate. The low bandwidth of the S/H circuit prevents accurate sampling of v.sub.in at higher frequencies. Other approaches are described in commonly assigned U.S. Pat. No. 5,172,019 entitled "Bootstrapped FET Sampling Switch" by Naylor et al. and commonly assigned U.S. Pat. No. 5,084,634 "Dynamic Input Sampling Switch for CDACs" by Gorecki. However, the bootstrapped circuits disclosed in these reference are unduly complex. They require supply voltages much greater than the input signals. Typically, these circuits operate from +15 volt and -15 volt power supplies with 5-10 volt input signals, and therefore have ample "head room" between the maximum amplitude input signal and the positive power supply level. Those skilled in the art know that this "head room" greatly simplifies the circuit design. For ADCs which are designed to operate from a single 5 volt power supply, there is no such ample "head room", and it is a major challenge to obtain the desired combination of adequate output signal levels, high circuit speed, low power dissipation, and simple circuit configurations that require relatively little chip area.
Various "bootstrap" circuits have been widely utilized since the early days of MOS technology, wherein a capacitor connected between the gate electrode and drain electrode of an MOS transistor is charged to provide an electrically "floating" gate voltage that differs from the source voltage by a constant voltage stored across the bootstrap capacitor. This results in a constant gate-to-source voltage being applied to the MOS transistor, irrespective of the source voltage. The constant gate-to-source voltage results in relatively constant channel resistance.